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Chapter 7: Pipelining & RISCs  What is pipelining? A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed. That is, several instructions are in the pipeline simultaneously, each at a different processing stage.
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The pipeline is divided into segments and each
segment can execute its operation concurrently with the other segments. When a
segment completes an operation, it passes the result to the next segment in the
pipeline and fetches the next operation from the preceding segment. The final
results of each instruction emerge at the end of the pipeline in rapid succession.
·
Although formerly a feature only of
high-performance and RISC -based microprocessors, pipelining is now
common in microprocessors used in personal computers. Intel's Pentium chip,
for example, uses pipelining to execute as many as six instructions
simultaneously.
·
Pipelining is also called pipeline
processing.
In a non-pipelined processing;
INSTRUCTION PIPELINING
Two Stage Instruction Pipeline
2 stage pipelining:
- fetch
- Execution
Six Stage
Pipelining
Stage 1: Fetch instruction (FI)
·
Read the next expected instruction into a buffer.
Stage 2: Decode instruction (DI)
·
Determine the opcode and the operand specifiers.
Stage 3: Calculate Operands (CO)
·
Calculate the effective address of each source
operand.
Stage 4: Fetch Operands (FO)
·
Fetch operand from memory. Operands in registers
need not to be fetched.
Stage 5: Execute instructions (EI)
·
Perform the indicated operation and store the
result.
Stage 6: Write operand (WO)
·
Store the result in memory.
Example
of 6 stage pipelining
Pipelining of Unequal Stages
v Always take
the largest of the stage delay to be the cycle time.
v No stage
overlaps and latency must be constant.
v Ensure that
instruction overlap is the same as the cycle time else get timing diagram is
wrong.
TIMING DIAGRAM :
Wrong timing diagram: Overlaps!
Wrong timing diagram: Latencies
not constant
Correct timing diagram
Pipeline
Performance
Total time
for equal stages
Total time
for unequal stages
Speedup
Calculating
speedup
Example 1: Based on the 2 stage timing diagram.
 Based on the above example 1 and 2, the speedup improves when the number of stage increase with the other values being same.
Example 3: Based n the 3 unequal stages example
Calculating
throughput
Pipelined Throughput= n/Tk (n)
Non-pipeline Throughput = n/To (n)
Limits to
Pipelining
The
next diagram illustrates a branch penalty. Instruction 3 is a conditional
branch to instruction 20, which is taken. As soon as it is executed in step 6,
the pipeline is flushed (instruction 3 is able to complete) and instructions
starting at #20 are loaded into the pipeline. Note that no instructions are
completed during cycles 7 through 10. Click on the image to see an animated
view and the bubble generated.
Hazards as
limitations to pipelining
Data dependencies example
A = B + C
D = E + A
C = G x H
CISC and
RISC
Characteristics
of CISC and RISC
RISC vs.
CISC
  
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